- Good knowledge on Verilog. Language proficiency is expected to be very high.
- SV exposure is a value addition.
- Good knowledge in circuit design basics
- Expert in integrating processor based SOC. Either the target could be ASIC or FPGA.
- Exposure to Linting, Formal verification is value addition.
- Simulation (RTL, GLS) is must.
- 2-3 Years
- Highly competitive to match experience and capability
Key skill Required
- RTL to GDS
- ASIC Design
- Design Engineer