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Job Description

Should have been involved in at least 20 multi-million gate chip tape outs
Should have worked on full chip/top level on at least 4 chips
Should have expertise in 14nm/10nm/7nm process nodes
Should have expertise in Logic/Physical Synthesis and Formal Verification
Should have understanding about internal scan, ATPG, BIST and JTAG
Should be doing hands-on work currently
Should be strong in TCL programming

Key skill Required


Designation

  • Project manager