Expertise in Floorplaning, Power planning, CTS.
Should be capable of handling block-level timing closure.
Should have knowledge on all low power & signoff checks, like MVRC/CLP, LEC/Formality, DRC, LVS, IR, EM.
Good scripting skills (TCL / SHELL).
Experience on low power implementation techniques is preferred.
Synopsys/Cadence tool experience is preferred.
Should be capable to lead a team of 5+ junior engineers. Should be able to provide any training/guidance that team members need
Bachelor degree in EC/EE is must or Mater degree in VLSI is preferred.
Good communication skills.
Key skill Required
- Project manager