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Job Description

You Implement RTL/Netlist-to-GDSII (Tools Cadence/Synopsys)
Synthesis & DFT Experience will be a plus
You Need Full exposure to all aspects of physical design flows like
You do Floor-planning – Block Level / Full Chip Level
You do Placement
You do CTS
You do Routing
Crosstalk (SI/Glitch) avoidance and fixes
Physical verification
Well versed with the timing closure methodologies
Well versed with timing DRV closure methodologies
You do ECO generation and predictable convergence
You do Parasitic Extraction
You do Calibre LVS/DRC/ERC and other Physical verification checks and fixes
RedHawk IR / EM checks and fixes
You have to well versed with the timing closure methodologies
You have to well versed with timing DRV closure methodologie

Key skill Required


Designation

  • Project manager