Job Description

Minimum 2+ year of experience in Synthesis and STA
Should have worked on several full chip designs both flat and hierarchical designs
Strong knowledge in RTL to Netlist handoff to Physical design team
Experience in low power/multi voltage design and understanding of UPF is preferred
Knowledge on Cadence based flows is preferred
Knowledge on DFT and Physical design is preferred
Synopsys/Cadence tool experience is preferred.
Good communication skills.

Key skill Required


  • Project manager