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Job Description

• Candidate should have a BS with 9+ years of experience or MS with 7+ years of experience in Electrical Engineering, Computer Engineering, or Electrical & Computer Engineering Experience with design principles and techniques in SoC and/or VLSI back-end design and/or integration covering 3 or more of: • Constraint understanding, generation, clock stamping and timing closure • Synthesis with Synopsys Design Compiler DCT • DFT, Scan Insertion, and coverage analysis • Multiple Power Domain Analysis using standard Power Formats UPF/CPF • Place and Route and clock tree synthesis • Static Timing Analysis

Key skill Required

  • STA

Designation

  • Project manager