PG : Masters in Electronics & Telecommunication/VLSI
Must be strong in basics of R,L,C, Network Theory, Signals & Systems, Control theory, Device fundamentals.
Must have hands-on working knowledge in analog circuit design, with special emphasis on Power Management (blocks like LDO, DCDC, POR/POK, Bandgap Reference).
Should be well-versed with industry standard EDA flows of Cadence/Mentor Graphics/Synopsys.
Basic knowledge of analog layout is needed. Knowledge of scripting languages (Perl, TCL, Skill, Ocean) is an added advantage.
Block level ECO implementation involving netlist level logical changes.
Scripting experience in Perl/TCL.
Excellent debugging skills in implementation issues and ability to come up with creative solutions.
Low power technologies exposure.
Technologies from 28nm and below.
Physical Verification experience in advance nodes.
Key skill Required
- Project manager